The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with integrated circuits such as those accessible from their back sides.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, different chip packaging techniques have been used. One technique is referred to as a dual in-line package (DIP) in which bonding pads are along the periphery of the device. Another technique, called controlled collapse chip connection or flip-chip packaging, uses the bonding pads and metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads. Each bump connects to a corresponding package inner lead. The resulting packages have a lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive-bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as pin grid array (PGA) package.
For BGA, PGA and other types of packages, once the die is attached to the package, the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip-chip.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the back side of the chip. This is challenging since the transistors are in a very thin layer (about 10 micrometers) of silicon buried under the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip-chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Techniques have been developed to access the circuit even though the circuit of the integrated circuit (IC) is buried under the bulk silicon. For example, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this means removing at least 625 microns of silicon before IR microscopy can be used.
Thinning the die for failure analysis of a flip-chip bonded IC is usually accomplished in two or three steps. The die is first thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the back side of the die using IR microscopy. Mechanical polishing is one method for global thinning. Using IR microscopy, an area is identified for accessing to a particular area of the circuit. Local thinning techniques such as laser microchemical etching are used to thin the silicon an area to a level that is thinner than the die size. One method for laser microchemical etching of silicon is accomplished by focusing a laser beam on the back side of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. A specific example silicon-removal process uses the 9850 SiliconEtcher(trademark) tool by Revise, Inc. (Burlington, Mass). This laser process is suitable for both local and global thinning by scanning the laser over a part of, or the whole, die surface.
During failure analysis, or for design debug, it is sometimes helpful to make electrical contact and probe certain circuit nodes on the circuit side or front side of the die. This is generally done by milling through the die to access the node, or milling to the node and subsequently depositing a metal to electrically access the node. These access holes often need to have high aspect ratios. For design debug, it is desirable to have the capability of cutting the interconnect lines and rerouting of the interconnect lines. Milling through silicon with fairly high aspect ratio trenches is slow and is almost impractical for silicon thickness greater than 10 microns. For these reasons, it is necessary to have a method and apparatus which will provide for controlled thinning flip-chip bonded IC devices to less than 10 micron thickness. It is also necessary to have a method where the thickness of the silicon can be determined with sufficient accuracy to avoid milling off the node to which access is being sought, since this could jeopardize further device analysis.
Accurately determining the thickness of the silicon is not readily achieved by thinning the back side to a distance above the package to which the die is attached. Various parts tolerances do not allow for such a simple approaching the circuit side of the die from the back side of the die. One tolerance issue revolves around keeping the height of solder ball contacts on the die substantially uniform for every packaged device of a particular type. Even though the solder ball contacts have a tolerance requirement, when the solder is reflowed to attach the die to a package, the amount of change in height due to solder reflow can vary by several microns. The thickness of the die between the circuit side and back side is also subject to tolerance differences. Since the thickness of the starting silicon wafer is a non-essential parameter for making a functioning die, typically the die thickness is not known to an accurate level. For instance, a typical die for a microprocessor may have a die thickness of 725xc2x115 microns. The end result is tolerance stacking due to the tolerances for the size of the solder balls, the height at which the die is attached and the thickness of the die. These tolerances stack up such that there can be tens of microns of difference in height from the top surface of the package to the top surface of the die among different packaged devices. This can be a significant problem, since the epitaxial layer is only between 2 and 10 microns thick. The thickness of the remaining silicon of a trench cannot be gauged by measuring from the top surface of the package to the bottom of the trench. Stack up of the tolerances of the various parts precludes simply xe2x80x9cmeasuring upxe2x80x9d from the package to which the die is attached to determine where the epitaxial layer containing the transistors begins. Simply put, such an approach is not adequately accurate to prevent ruining the circuitry or transistors that must be analysed or debugged. Once the circuitry or transistors are ruined, analysis or debugging is frustrated.
The present invention provides methods and apparatuses for detecting the location of a portion of the active circuitry in an integrated circuit, for example, near the circuit side of an integrated circuit die. In this manner, guesswork as to the location of the circuitry while the back side of a die is being removed is eliminated, and the ability to navigate during the milling process is improved. Consequently, failure analysis and debugging of the circuitry associated with a particular integrated circuit is improved. Furthermore, when the position of the circuitry with respect to the milling progress is known or can be determined from the back side removal of the silicon, getting to the circuitry can be accomplished in less time.
The difficulty in locating and milling to a selected region of a semiconductor device as discussed above is lessened by the use of the invention herein. In one example embodiment, the present invention involves the use of a method for milling the substrate of a semiconductor device and exposing a selected region in the substrate, wherein the semiconductor device has a circuit side and a back side, and the back side has at least two layers. The back side surface of the semiconductor device is marked with a laser over a selected region in the substrate. A milling device, such as a focused ion beam (FIB), is then directed at the marked area of the back side of the device. Substrate is removed, thereby exposing the selected region.
According to another example embodiment, a semiconductor device used in milling and exposing a selected region in the device. The semiconductor device comprises: a circuit side and a back side; and a laser-formed marker on a surface of the back side of the device, wherein the marker is used for alignment during milling to access the selected region within the device.
According to another example method for milling the substrate of a semiconductor device, the present invention involves means for marking the back side surface of the semiconductor device over a selected region in the substrate. Once the back side surface is marked, means for directing over the marked area of the back side of the device are used. Finally, means for removing the substrate and exposing the selected region in the substrate complete the milling method.
In another embodiment, the invention includes a semiconductor device for use in the semiconductor industry, wherein the semiconductor device includes a circuit side and a back side. The device further comprises a marker on the surface of the back side of the device, wherein the marker may be used, for example, for alignment of a milling device with selected regions within the substrate of the semiconductor device.
In still another embodiment, the invention includes an apparatus for milling the substrate of a semiconductor device and exposing a selected region in the substrate, wherein the semiconductor device includes a circuit side and a back side. The apparatus comprises means for aligning with a selected region within the substrate, means for marking the back side surface of the semiconductor device, and means for removing the substrate.
The methods and apparatus described above significantly improve the manufacture of semiconductor devices. This invention provides the ability to accurately control milling processes used with semiconductor devices, improving the ability to test circuits, troubleshoot defective circuits, and the overall manufacture of such devices. The guesswork and difficulties formerly required with alignment of the milling process are reduced or eliminated.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.